Silicon Design Engineer for Google - RTL and RISC-V

Silicon Design Engineer – RISC-V / RTL at Google via Insight Global

Pay: $70-90/HR

Duration: Long Term Contract - 12-month renewal increments

Location: HYBRID onsite in NYC

We are seeking a Silicon Design Engineer to support the development of next-generation processor technology. This role is focused on CPU microarchitecture, RTL development, and optimization of high-performance silicon designs.

Responsibilities:

• Design and implement RTL for RISC-V processor cores and subsystems
• Develop and review CPU microarchitecture specifications
• Work on pipelines, caches, execution units, memory subsystems, and related processor logic
• Optimize designs for power, performance, and area (PPA)
• Support lint, simulation, synthesis, verification, and design signoff
• Debug RTL and collaborate with architecture, verification, and software teams

Qualifications:

• Hands-on RTL design experience using SystemVerilog, Verilog, VHDL, Chisel, or similar
• RISC-V experience
• Understanding of CPU/processor architecture and microarchitecture
• Experience with ASIC, SoC, CPU, GPU, or accelerator design
• Familiarity with synthesis and RTL design flows

Preferred:

• CPU core or processor subsystem design
• Synopsys VCS, Design Compiler, or similar tools
• Experience with PPA optimization and silicon tapeout

The final rate offered will depend on the candidate’s experience, skills, qualifications, geographic location, and other job-related factors. Benefits and other compensation may vary based on employment status and eligibility.