RISC-V Design Verification Engineer (Mid-Staff)

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Job Overview

The RISC-V Design Verification Engineer at Andes Technology Corporation will play a crucial role in ensuring the functionality and reliability of RISC-V processor designs. This mid-staff level position involves working closely with design engineering teams to establish comprehensive verification methodologies, develop test plans, and execute rigorous testing protocols. The engineer will be expected to analyze design specifications, identify potential issues, and contribute to the continuous improvement of verification processes. The successful candidate will leverage their expertise in verification technologies and methodologies to enhance the overall quality of the company's RISC-V products.

Job Responsibilities

• Develop and implement verification plans for RISC-V processor designs.
• Collaborate with hardware engineers to review design specifications and functional requirements.
• Utilize SystemVerilog and UVM for creating testbenches and test cases.
• Perform thorough simulations and debugging to ensure compliance with design objectives.
• Contribute to the development of verification methodologies and best practices.
• Document verification processes and results for quality assurance.
• Participate in design reviews and provide feedback on architectural choices.
• Assist in the integration and validation of design changes.

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• 3+ years of experience in ASIC design verification, preferably in RISC-V or similar architectures.
• Strong proficiency in SystemVerilog and verification methodologies (UVM, OVM).
• Experience with simulation tools such as Cadence Xcelium, Mentor Graphics ModelSim, or equivalent.
• Solid understanding of digital design concepts and writing RTL code.
• Familiarity with hardware debugging tools and techniques.
• Excellent analytical, problem-solving, and communication skills.

Technologies & Tools

The RISC-V Design Verification Engineer will utilize a variety of advanced technologies and tools in their day-to-day work. Key technologies include SystemVerilog, Universal Verification Methodology (UVM), and various simulation and debugging tools such as Cadence Xcelium and Mentor Graphics ModelSim. The position will also require the use of version control systems like Git for code management, as well as familiarity with scripting languages such as Python or Tcl for automation tasks.

Ideal Candidates

Ideal candidates for the RISC-V Design Verification Engineer position will possess a blend of technical expertise and soft skills. They should be detail-oriented, capable of working effectively under pressure, and driven by a passion for innovation in processor design. Strong collaboration skills are essential, as the role requires extensive interaction with cross-functional teams. Candidates should also exhibit a proactive attitude towards learning and improvement, showing an eagerness to stay updated with the latest advancements in RISC-V architecture and verification technologies.