FPGA Design/Verification Engineer with Active Secret Security Clearance

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Job Overview

GeoLogics Corporation is seeking a skilled FPGA Design/Verification Engineer with an Active Secret Security Clearance to join our dynamic team. This position entails the design, development, and verification of FPGA applications while ensuring adherence to project specifications and security protocols. The successful candidate will collaborate closely with cross-functional teams to deliver innovative solutions, contributing to projects that play a critical role in our national defense and aerospace initiatives.

Job Responsibilities

• Design and implement FPGA architectures and algorithms per project requirements.
• Conduct thorough verification and validation of FPGA designs, including simulations and hardware testing.
• Collaborate with hardware and software teams to ensure integration of designs with system architecture.
• Utilize industry-standard tools for synthesis, place-and-route, and timing analysis.
• Prepare and maintain detailed design documentation, including specifications and test plans.
• Support troubleshooting and debugging of FPGA-related issues in a lab environment.
• Participate in design reviews and provide constructive feedback to peers.
• Stay current with technological advancements in FPGA development and verification methodologies.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field.
• Minimum of 3 years of experience in FPGA design and verification.
• Proficiency in VHDL or Verilog for FPGA programming.
• Experience with FPGA development tools such as Xilinx Vivado or Intel Quartus.
• Strong understanding of digital design principles and methods.
• Active Secret Security Clearance is required.
• Excellent problem-solving skills and attention to detail.
• Effective communication skills, both written and verbal.

Technologies & Tools

The FPGA Design/Verification Engineer will utilize a range of technologies and tools in this role, including but not limited to FPGA development software such as Xilinx Vivado and Intel Quartus, simulation tools like ModelSim or QuestaSim, along with embedded C/C++ development environments. Familiarity with version control systems, such as Git, and hardware description languages (HDLs) like VHDL or Verilog will be crucial for successful project execution.

Ideal Candidates

Ideal candidates for the FPGA Design/Verification Engineer position at GeoLogics Corporation will possess a strong analytical mindset and an unwavering attention to detail. They will be highly motivated individuals who thrive in a collaborative environment and are committed to delivering high-quality results under tight deadlines. A proactive approach to problem-solving and a passion for staying abreast of technological developments in the field of FPGA design and verification will further distinguish successful applicants.