Silicon Physical Design Engineer III

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Written by AI from the job title and company, not by Actalent, so some details may not match this job. The employer's own page has the real description.

Job Overview

As a Silicon Physical Design Engineer III at Actalent, you will engage in complex design tasks that encompass the implementation of floorplanning, placement, and routing processes for silicon chip designs. You will collaborate closely with cross-functional teams to optimize designs for performance, power, and area while ensuring manufacturability and testability. This role demands a strong foundation in physical design methodologies and the ability to troubleshoot and resolve design issues efficiently, contributing to the successful delivery of high-quality silicon solutions.

Job Responsibilities

• Develop and execute physical design methodologies for advanced silicon chips.
• Perform floorplanning, placement, and clock tree synthesis to enhance design performance.
• Conduct design rule checking (DRC) and layout versus schematic (LVS) verification.
• Collaborate with RTL, verification, and test teams to improve design accuracy and functionality.
• Analyze and optimize design for power, performance, and area (PPA) metrics.
• Utilize scripting languages to automate design tasks and improve productivity.
• Participate in design review meetings and provide technical insights to team members.

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
• A minimum of 5 years of experience in physical design for silicon chips.
• Proficient in industry-standard tools such as Cadence, Synopsys, and Mentor Graphics.
• Strong understanding of digital circuits, timing analysis, and silicon fabrication processes.
• Experience in using scripting languages such as TCL, Perl, or Python.
• Ability to work collaboratively in a team environment while managing multiple tasks.

Technologies & Tools

In this role, the candidate will leverage a suite of technologies and tools essential for silicon physical design processes. Key tools include Cadence Innovus for place-and-route automation, Synopsys IC Compiler for design implementation, and Mentor Graphics Calibre for DRC and LVS verification. Additionally, proficiency in scripting and automation tools will be required to streamline workflows and improve design efficiency.

Ideal Candidates

The ideal candidate for the Silicon Physical Design Engineer III position is a detail-oriented individual with a strong analytical mindset and excellent problem-solving skills. They should possess a proactive attitude toward addressing design challenges and demonstrate a commitment to continuous learning and professional growth. Strong communication skills are essential for effective collaboration within multidisciplinary teams, along with the ability to work under pressure and meet project deadlines. A passion for innovation in technology and an eagerness to contribute to cutting-edge silicon solutions will set the successful candidate apart.