Sr. ASIC / SoC Digital RTL Design Engineer

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Job Overview

The Sr. ASIC / SoC Digital RTL Design Engineer at ASICSoft will play a pivotal role in the design and implementation of advanced ASIC and SoC solutions. The successful candidate will be responsible for leading RTL design projects from conception through verification, collaborating closely with cross-functional teams to ensure high-quality deliverables. This position demands a strong understanding of digital design principles, methodologies, and tools, as well as the ability to troubleshoot and optimize designs for performance, area, and power consumption.

Job Responsibilities

• Design and develop digital RTL for complex ASIC and SoC architectures.
• Collaborate with the verification team to create verification plans and ensure thorough testing of designs.
• Perform RTL synthesis and optimizations targeting area, speed, and power.
• Conduct functional simulations and debug RTL issues using established methodologies and tools.
• Participate in architecture and design reviews, providing input on potential improvements and optimizations.
• Support integration activities and resolve issues arising during the implementation and testing phases.
• Mentor junior engineers and contribute to their professional development.

Qualifications

• B.S. or M.S. degree in Electrical Engineering, Computer Engineering, or a related field.
• A minimum of 5 years of experience in digital RTL design for ASICs or SoCs.
• Proficiency in HDLs such as Verilog and VHDL.
• Hands-on experience with synthesis tools (e.g., Synopsys, Cadence) and EDA tools for simulation and verification.
• Solid understanding of digital logic design and deep knowledge of low-power design techniques.
• Experience with scripting languages such as Python or Tcl.
• Strong analytical and problem-solving skills with attention to detail.

Technologies & Tools

This position requires proficiency in various technologies and tools, including but not limited to HDL programming languages (Verilog, VHDL), simulation tools (ModelSim, Questa), synthesis tools (Synopsys Design Compiler, Cadence Genus), and verification methodologies (UVM, SystemVerilog). Familiarity with software tools for power analysis (PrimeTime, Power Compiler) and debugging (SignalTap, Logic Analyzer) will also be beneficial. The role may involve the use of scripting languages for automation and tool integration.

Ideal Candidates

The ideal candidate for the Sr. ASIC / SoC Digital RTL Design Engineer role possesses a strong technical foundation combined with excellent communication skills. They should exhibit a proactive and innovative mindset, embracing challenges and striving for excellence in designs. Being a team player, the candidate will demonstrate the ability to work collaboratively across disciplines, mentoring others while also being open to feedback. A passion for continuous learning and keeping abreast of the latest trends in digital design technologies will be highly valued.