ASIC Verification Engineer- UVM / RISC-V / System Verilog

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Job Overview

The ASIC Verification Engineer will play a vital role in the design and verification of advanced ASIC systems, focusing on UVM methodology, RISC-V architecture, and System Verilog coding. The successful candidate will be responsible for developing and implementing test plans, verifying functional specifications, debugging designs, and collaborating with cross-functional teams to ensure the highest quality deliverables. This position offers an opportunity to work with cutting-edge technology in a dynamic and innovative environment.

Job Responsibilities

• Develop and execute comprehensive verification plans for ASIC designs using UVM methodology.
• Create and maintain test environments and test benches in System Verilog.
• Collaborate with design engineers to understand specifications, requirements, and design changes.
• Identify and debug logical issues in RTL designs through rigorous testing and simulation.
• Work on RISC-V architecture compliance and verification, ensuring designs meet industry standards.
• Generate detailed verification reports and documentation for project stakeholders.
• Support design reviews and provide feedback to enhance design quality and performance.

Qualifications

• Bachelor’s or Master's degree in Electrical Engineering, Computer Engineering, or related field.
• Proven experience in ASIC verification using UVM, with a strong understanding of verification flow.
• Proficient in System Verilog and familiar with RISC-V architecture.
• Hands-on experience in simulation and debugging tools such as ModelSim or Synopsys VCS.
• In-depth knowledge of digital design principles and verification methodologies.
• Ability to work effectively within cross-functional teams as well as independently.
• Strong communication skills, both written and verbal.

Technologies & Tools

The position heavily utilizes modern verification tools and methodologies, including Universal Verification Methodology (UVM) for testbench development, System Verilog for design and verification, and specialized simulation tools like ModelSim and Synopsys VCS. Familiarity with hardware description languages (HDLs) and compliance standards related to RISC-V architecture is also necessary for success in this role.

Ideal Candidates

Ideal candidates for the ASIC Verification Engineer position will possess a strong technical acumen and a proactive approach to problem-solving. They should demonstrate a keen attention to detail, the ability to work under pressure, and a passion for innovation in semiconductor technology. Furthermore, having strong interpersonal skills and the ability to communicate complex concepts clearly will be critical in fostering successful collaboration with team members.