ASIC Verification Engineer- UVM / RISC-V / System Verilog

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Job Overview

The ASIC Verification Engineer will play a vital role in the verification of complex ASIC designs, specifically focusing on RISC-V architectures and utilizing the UVM methodology with SystemVerilog. This position involves collaborating with cross-functional teams to ensure the functionality and reliability of designs, developing verification plans, writing testbenches, and executing tests to validate designs against specifications. The candidate will also be responsible for debugging and troubleshooting any issues that arise during the verification process, maintaining high standards of quality and efficiency throughout the project lifecycle.

Job Responsibilities

• Develop and implement verification plans for ASIC designs using UVM methodology.
• Create and maintain SystemVerilog testbenches for RISC-V architecture.
• Execute simulation and validation tests against design specifications.
• Identify, isolate, and debug design and verification issues effectively.
• Perform code reviews and participate in design verification team meetings.
• Generate coverage reports to assess verification progress and completeness.
• Collaborate with design engineers to understand design features and requirements.
• Contribute to continuous improvement of verification methodologies and practices.

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
• Minimum of 3 years of experience in ASIC verification or related roles.
• Proficiency in SystemVerilog and UVM methodologies.
• Strong understanding of RISC-V architecture and instruction set details.
• Experience with simulation tools such as ModelSim, VCS, or equivalent.
• Familiarity with scripting languages (such as Perl or Python) for automation.
• Excellent analytical and troubleshooting skills.
• Ability to work collaboratively in a team-oriented environment.

Technologies & Tools

The ASIC Verification Engineer position primarily utilizes SystemVerilog and the Universal Verification Methodology (UVM) to facilitate the verification process. Familiarity with RISC-V architecture is essential, along with experience using various simulation tools such as ModelSim, VCS, or similar environments. Additional proficiency in scripting languages such as Python or Perl for automation tasks will be beneficial for streamlining verification workflows.

Ideal Candidates

Ideal candidates for the ASIC Verification Engineer role will demonstrate a strong technical foundation in ASIC verification combined with excellent problem-solving abilities. They should possess a keen attention to detail and a proactive attitude towards learning and implementing new verification techniques. Effective communication skills, both verbal and written, are critical, as is the ability to work collaboratively within a multidisciplinary team. A commitment to delivering high-quality results and a passion for innovation in semiconductor technology will greatly enhance their fit for this position.